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19-5028; Rev 1; 2/10
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
General Description
The MAX16067 flash-configurable system manager monitors and sequences multiple system voltages. The MAX16067 manages up to six system voltages simultaneously. The MAX16067 integrates an analog-to-digital converter (ADC) and configurable outputs for sequencing power supplies. Device configuration information, including overvoltage and undervoltage limits, time delay settings, and the sequencing order is stored in nonvolatile flash memory. During a fault condition, fault flags and channel voltages can be automatically stored in the nonvolatile flash memory for later readback. The internal 1% accurate, 10-bit ADC measures each input and compares the result to one overvoltage and one undervoltage limit. A fault signal asserts when a monitored voltage falls outside the set limits. The MAX16067 supports a power-supply voltage of up to 14V and can be powered directly from the 12V intermediate bus in many systems. The integrated sequencer provides precise control over the power-up and power-down order of up to six power supplies. Three outputs (EN_OUT1 to EN_OUT3) are configurable with charge-pump outputs to directly drive external n-channel MOSFETs. The MAX16067 includes six programmable generalpurpose inputs/outputs (GPIOs). GPIOs are flash configurable as a fault output, as a watchdog input or output, or as a manual reset. The MAX16067 features nonvolatile fault memory for recording information during system shutdown events. The fault logger records a failure in the internal flash and sets a lock bit protecting the stored fault data from accidental erasure. An SMBusTM or a JTAG serial interface configures the MAX16067. The MAX16067 is available in a 32-pin, 5mm x 5mm, TQFN package and is fully specified over the -40NC to +85NC extended temperature range. S Operates from 2.8V to 14V S 1% Accurate, 10-Bit ADC Monitors 6 Voltage Inputs S Analog EN Monitoring Input S 6 Monitored Inputs with Overvoltage and Undervoltage Limits S Nonvolatile Fault Event Logger S Power-Up and Power-Down Sequencing Capability S 6 Outputs for Sequencing/Power-Good Indicators S 3 Configurable Charge-Pump Outputs S Six General-Purpose Inputs/Outputs Configurable as: Dedicated Fault Output Watchdog Timer Function Manual Reset SMBus Alert Fault Propagation Input/Output S SMBus and JTAG Interface S Supports Cascading with MAX16065/MAX16066 S Flash-Configurable Time Delays and Thresholds S -40NC to +85NC Extended Operating Temperature Range
Features
MAX16067
Applications
Networking Equipment Telecom Equipment (Base Stations, Access) Storage/Raid Systems Servers
Typical Operating Circuit appears at end of data sheet.
Ordering Information/Selector Guide
PART PIN-PACKAGE VOLTAGEDETECTOR INPUTS GENERAL-PURPOSE INPUTS/OUTPUTS 6 SEQUENCING OUTPUTS 6
MAX16067ETJ+ 32 TQFN-EP* 6 Note: This device is specified over the -40NC to +85NC extended temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. SMBus is a trademark of Intel Corp.
_______________________________________________________________ Maxim Integrated Products 1
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
ABSOLUTE MAXIMUM RATINGS
VCC to GND ....................................................-0.3V to +15V MON_, SCL, SDA, A0 to GND ................................-0.3V to +6V EN, TCK, TMS, TDI to GND ....................................-0.3V to +4V TDO to GND ............................................-0.3V to (VDBP + 0.3V) EN_OUT1, EN_OUT2, EN_OUT3 (configured as open-drain) to GND ..................-0.3V to +15V EN_OUT1, EN_OUT2, EN_OUT3 (configured as charge pump) to GND ..............-0.3V to +15V EN_OUT4, EN_OUT5, EN_OUT6, RESET, GPIO_ (configured as open-drain) to GND. ....................-0.3V to +6V EN_OUT_, RESET, GPIO_ (configured as push-pull) to GND .................................................-0.3V to (VDBP + 0.3V) DBP, ABP to GND .......................................-0.3V to minimum of (4V and (VCC + 0.3V)) Continuous Current (all other pins) ................................. Q20mA Continuous Current (GND, pin 5).................................... Q30mA Continuous Power Dissipation (TA = +70NC) 32-Pin TQFN (derate 34.5mW/NC above +70NC) ..... 2759mW* Thermal Resistance (Note 1) BJA ................................................................................29NC/W BJC .................................................................................2NC/W Operating Temperature Range .......................... -40NC to +85NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
*As per JEDEC 51 Standard, Multilayer Board (PCB). Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.8V to 14V, TA = TJ = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.) (Note 2) PARAMETER Operating Voltage Range Undervoltage Lockout Undervoltage Lockout Hysteresis Minimum Flash Operating Voltage SYMBOL VCC VUVLO UVLOHYS VFLASH ICC1 Supply Current ICC2 Minimum voltage on VCC to ensure flash erase and write operations No load on any output No load on any output, during flash writing cycle VCC = VABP = VDBP = 3.6V (Note 3) DBP Regulator Voltage ABP Regulator Voltage Boot Time Flash Writing Time Internal Timing Accuracy ADC Resolution Gain Error Offset Error Integral Nonlinearity 2 ADCGAIN ADCOFF ADCINL TA = +25NC TA = -40NC to +85NC 10 0.35 0.75 1.50 1 Bits % LSB LSB VDBP VABP tBOOT VCC = 5V, CDBP = 1FF, no load VCC = 5V, CABP = 1FF, no load VCC > VUVLO 8-byte word (Note 4) -10 2.8 2.85 3 3 100 122 +10 2.7 2.8 7.7 4 14 5 3.2 3.15 200 V V Fs ms % mA CONDITIONS RESET output asserted low Minimum voltage on VCC to ensure the device is flash configurable 55 MIN 1.2 2.8 14 2.7 TYP MAX UNITS V V mV V
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = TJ = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.) (Note 2) PARAMETER Differential Nonlinearity ADC Total Monitoring Cycle Time SYMBOL ADCDNL tCYCLE Monitoring all 6 inputs, no MON_ fault detected MON_ range set to `00' ADC MON_ Ranges ADCRNG MON_ range set to `01' MON_ range set to `10' MON_ range set to `00' ADC LSB Step Size ADC Input Leakage Current ENABLE INPUT (EN) EN Input-Voltage Threshold EN Input Current EN Input-Voltage Range OUTPUTS (EN_OUT_, RESET, GPIO_) ISINK = 2mA Output Voltage Low VOL ISINK = 10mA, GPIO_ only VCC = 1.2V, ISINK = 100FA (RESET only) Maximum Output Sink Current Output-Voltage High (Push-Pull) Output-Voltage High (EN_OUT1, EN_OUT2, EN_OUT3 Configured as Charge Pumps) EN_OUT_ Pullup Current (Charge Pump) Output Leakage Current (Open Drain) INPUTS (A0, GPIO_) Input Logic-Low Input Logic-High WDI Pulse Width MR Pulse Width SMBus INTERFACE Logic-Input Low Voltage Logic-Input High Voltage Input Leakage Current Output Sink Current Input Capacitance VOL CIN VIL VIH Input voltage falling Input voltage rising VCC shorted to GND, VMON_ = 0 or 6V ISINK = 3mA 5 2.0 -1 +1 0.4 0.8 V V FA V pF 3 VIL VIH tWDI tMR 2.0 100 2 0.8 V V ns Fs VOH Total current into EN_OUT_, RESET, GPIO_, VCC = 3.3V ISOURCE =100FA 2.4 0.4 0.7 0.3 30 mA V V VTH_EN_R VTH_EN_F IEN EN voltage rising EN voltage falling 1.195 -0.5 0 1.24 1.215 1.235 +0.5 3.6 V FA V ADCLSB MON_ range set to `01' MON_ range set to `10' 24 5.552 2.776 1.388 5.42 2.71 1.35 1 FA mV V CONDITIONS MIN TYP MAX 1 30 UNITS LSB Fs
MAX16067
VOH_CP
IEN_OUT_= 1FA
11
11.7
13
V
ICH_UP IOUT_LKG
VEN_OUT_ = 1V
5.4
7.9 1
FA FA
EN_OUT1, EN_OUT2, EN_OUT3 > 11.8V
5
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = TJ = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.) (Note 2) PARAMETER SMBus TIMING Serial-Clock Frequency Bus Free Time Between STOP and START Condition START Condition Setup Time START Condition Hold Time STOP Condition Setup Time Clock Low Period Clock High Period Data Setup Time Output Fall Time Data Hold Time Pulse Width of Spike Suppressed SMBus Timeout JTAG INTERFACE TDI, TMS, TCK Logic-Low Input Voltage TDI, TMS, TCK Logic-High Input Voltage TDO Logic-Output Low Voltage TDO Logic-Output High Voltage TDI, TMS Pullup Resistors I/O Capacitance TCK Clock Period TCK High/Low Time TCK to TMS, TDI Setup Time TCK to TMS, TDI Hold Time TCK to TDO Delay TCK to TDO High-Z Delay VIL VIH VOL_TDO VOH_TDO RJPU CI/O t1 t2, t3 t4 t5 t6 t7 50 15 15 500 500 500 Input voltage falling Input voltage rising ISINK = 3mA ISOURCE = 200FA Pullup to DBP 2.4 30 50 5 1000 65 2.0 0.4 0.8 V V V V kI pF ns ns ns ns ns ns fSCL tBUF tSU:STA tHD:STA tSU:STO tLOW tHIGH tSU:DAT tOF tHD:DAT tSP tTIMEOUT SMBCLK time low for reset 22 10pF P CBUS P 400pF From 50% SCL falling to SDA change Receive Transmit 0.15 0.3 250 35 0.9 1.3 0.6 0.6 0.6 1.3 0.6 100 250 400 kHz Fs Fs Fs Fs Fs Fs ns ns Fs ns ms SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 2: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA = +25NC and TA = +85NC. Specifications at TA = -40NC are guaranteed by design. Note 3: For VCC of 3.6V or lower, connect VCC, DBP, and ABP together. For higher supply applications, connect only VCC to the supply rail. Note 4: Applies to RESET (except for reset timeout period of 25Fs), fault, autoretry, sequence delays, and watchdog timeout.
4
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
SDA
tSU:DAT
tBUF tLOW tHD:DAT tSU:STA tHD:STA tSU:STO
SCL
tHIGH
tHD:STA
tR
START CONDITION
tF
REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 1. SMBus Timing Diagram
t1 t2 t3
TCK
t4
t5
TDI, TMS t6 t7 TDO
Figure 2. JTAG Timing Diagram
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Typical Operating Characteristics
(Typical values are at VCC = 3.3V, TA = +25NC.)
VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE
MAX16067 toc01
NORMALIZED MON_THRESHOLD vs. TEMPERATURE
MAX16067 toc02
NORMALIZED EN THRESHOLD vs. TEMPERATURE
1.040 NORMALIZED EN THRESHOLD 1.025 1.010 0.995 0.980 0.965 0.950
MAX16067 toc03
4.0 3.5 3.0 ICC (mA) 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8 VCC (V) 10 12
TA = -40C ABP AND DBP REGULATORS ACTIVE TA = +25C ABP AND DBP CONNECTED TO VCC TA = +85C
1.055 NORMALIZED MON_ THRESHOLD 1.040 1.025 1.010 0.995 0.980 0.965 0.950 -40 -20 0 20 40 60 80 TEMPERATURE (C) 5.6V RANGE HALF-SCALE PUV THRESHOLD
1.055
14
-40
-20
0
20
40
60
80
TEMPERATURE (C)
TRANSIENT DURATION vs. THRESHOLD OVERDRIVE (EN)
MAX16067 toc04
NORMALIZED TIMING ACCURACY vs. TEMPERATURE
MAX16067 toc05
TRANSIENT DURATION vs. MON_ DEGLITCH
80 TRANSIENT DURATION (us) 70 60 50 40 30 20 10 0
MAX16067 toc06
35 30 TRANSIENT DURATION (s) 25 20 15 10 5 0 1 10 EN OVERDRIVE (mV)
1.055 1.040 NORMALIZED SLOT DELAY 1.025 1.010 0.995 0.980 0.965 0.950
90
100
-40
-20
0
20
40
60
80
2
4
8
16
TEMPERATURE (C)
DEGLITCH VALUE
MR TO RESET PROPAGATION DELAY vs. TEMPERATURE
1000 900 800 DELAY (ns) VOUT (V) 700 600 500 400 300 200 100 -40 -20 0 20 40 60 80 TEMPERATURE (C) MIN
MAX16067 toc07
OUTPUT VOLTAGE vs. SINK CURRENT (OUT = LOW)
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 5 10 ISINK (mA) 15 20 RESET, GPIO_, AND EN_OUT4- EN_OUT6 EN_OUT1- EN_OUT3
MAX16067 toc08
1100 MAX
0.40
6
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Typical Operating Characteristics (continued)
(Typical values are at VCC = 3.3V, TA = +25NC.)
MAX16067
OUTPUT-VOLTAGE HIGH vs. SOURCE CURRENT (CHARGE-PUMP OUTPUT)
MAX16067 toc09
OUTPUT-VOLTAGE HIGH vs. SOURCE CURRENT (PUSH-PULL OUTPUT)
MAX16067 toc10
INTEGRAL NONLINEARITY vs. CODE
0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 CODE (LSB)
MAX16067 toc11 MAX16067 toc13
14 12 10 VOUT (V)
3.4 3.3 3.2 3.1
VOUT (V)
1.0
RESET GPIO_
8 6 4 2 0 0 1 2 3 4 5 6 7 8 ISOURCE (A)
3.0 2.9 2.8 2.7 2.6 2.5 2.4 0 200 400 EN_OUT1, EN_OUT2, EN_OUT3
600
800
1000
1200
ISOURCE (A)
DIFFERENTIAL NONLINEARITY vs. CODE
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 CODE (LSB)
MAX16067 toc12
FET TURN_ON WITH CHARGE PUMP
1.0
VEN_OUT1 5V/div
IOUT 1A/div VOUT 5V/div 100ms/div
SEQUENCING
MAX16067 toc14
RESET OUTPUT CURRENT vs. VCC SUPPLY VOLTAGE
ABP AND DBP CONNECTED TO VCC
MAX16067 toc15
25 20
OUTPUT CURRENT (mA)
VEN_OUT1 2V/div VEN_OUT2 2V/div VEN_OUT3 2V/div VEN_OUT4 2V/div
15 10 5
ABP AND DBP REGULATORS ACTIVE
VRESET = 0.3V
200s/div
0 0 2 4 6 8 10 12 14 VCC (V)
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Pin Configuration
EN_OUT1 18 EN_OUT2 17 16 15 14 13 EN_OUT3 EN_OUT4 EN_OUT5 EN_OUT6 TMS TCK TDI TDO 12 11 + 1 GPIO3 2 GPIO4 3 GPIO5 4 GPIO6 5 GND 6 AO *EP 10 9 7 SCL 8 SDA
MON1
GND
ABP
VCC
DBP 20
24 MON2 25 MON3 26 MON4 27 MON5 28 MON6 29 RESET 30 GPIO1 31 GPIO2 32
23
22
21
MAX16067
TQFN
*CONNECT EXPOSED PAD TO GND.
EN 19
TOP VIEW
Pin Description
PIN 1-4, 31, 32 5, 23 6 7 8 9 10 11 12 NAME GPIO3-GPIO6, GPIO1, GPIO2 GND A0 SCL SDA TDO TDI TCK TMS EN_OUT6- EN_OUT1 EN FUNCTION General-Purpose Inputs/Outputs. Each GPIO_ can be configured to act as an input, a push-pull output, an open-drain output, or a special function. Ground. Connect all GNDs together. Four-State SMBus Address. Address is sampled upon POR. SMBus Serial-Clock Input SMBus Serial-Data Open-Drain Input/Output JTAG Test Data Output JTAG Test Data Input JTAG Test Clock JTAG Test Mode Select Outputs. Set EN_OUT_ with an active-high/active-low logic and with push-pull or open-drain configuration. EN_OUT_ can be asserted by a combination of MON_ voltages configurable through the flash. EN_OUT1-EN_OUT3 can be configured with a charge-pump output (+12V above GND) that can drive an external n-channel MOSFET. All EN_OUT_ can be configured as GPIOs. Analog Enable Input. All outputs deassert when VEN is below the enable threshold.
13-18
19
8
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Pin Description (continued)
PIN 20 21 22 24-29 30 -- NAME DBP VCC ABP MON1-MON6 RESET EP FUNCTION Digital Bypass. All push-pull outputs are referenced to DBP. Bypass DBP with a 1FF capacitor to GND. Power-Supply Input. Bypass VCC to GND with a 10FF ceramic capacitor. Analog Bypass. Bypass ABP to GND with a 1FF ceramic capacitor. Monitor Voltage Inputs. Set the monitor voltage range through the configuration registers. Measured values are written to the ADC registers and can be read back through the SMBus or JTAG interface. Configurable Reset Output Exposed Pad. Internally connected to GND. Connect to ground, but do not use EP as the main ground connection.
MAX16067
Functional Diagram
VCC ABP DBP REF EN DECODE LOGIC REG ALERT FAULT MR EXTFAULT WDI WATCHDOG WDO TIMER GPIO CONTROL GPIO1 GPIO2 GPIO3 GPIO6 GPIO4 GPIO5 EN_OUT1- EN_OUT6
VTH_EN
MON1 MON2 MON3 MON4 MON5 MON6 VOLTAGE AND SCALING MUX 10-BIT ADC (SAR) ADC REGISTERS DIGITAL COMPARATORS
MAX16067
SEQUENCER STATE MACHINE RESET OUTPUT LOGIC
RESET
RAM REGISTERS
SMBus INTERFACE AO SCL SDA
FLASH REGISTERS GND
JTAG INTERFACE TDO TDI TCK TMS
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Detailed Description
The MAX16067 manages up to six system power supplies. After boot-up, if EN is high and the software-enable bit is set to `1,' a power-up sequence begins based on the configuration stored in flash and the EN_OUT_s are controlled accordingly. When the power-up sequence is successfully completed, the monitoring phase begins. An internal multiplexer cycles through each MON_ input. At each multiplexer stop, the 10-bit ADC converts the monitored analog voltage to a digital result and stores the result in a register. Each time a conversion cycle (5Fs, max) completes, internal logic circuitry compares the conversion results to the overvoltage and undervoltage thresholds stored in memory. When a result violates a programmed threshold, the conversion can be configured to generate a fault. GPIO_ can be programmed to assert on combinations of faults. Additionally, faults can be configured to shut off the system and trigger the nonvolatile fault logger, which writes all fault information automatically to the flash and write-protects the data to prevent accidental erasure. The MAX16067 contains both SMBus and JTAG serial interfaces for accessing registers and flash. Use only one interface at any given time. For more information on how to access the internal memory through these interfaces, see the SMBus-Compatible Serial Interface and JTAG Serial Interface sections. The memory map is divided into three pages with access controlled by special SMBus and JTAG commands. The factory-default values at POR (power-on reset) for all RAM registers are `0's. POR occurs when VCC reaches the undervoltage-lockout threshold (UVLO) of 2.7V (max). At POR, the device begins a boot-up sequence. During the boot-up sequence, all monitored inputs are masked from initiating faults and flash contents are copied to the respective register locations. During bootup, the MAX16067 is not accessible through the serial interface. The boot-up sequence takes up to 150Fs, after which the device is ready for normal operation. RESET is asserted low up to the boot-up phase after which it assumes its programmed active state. RESET remains active for its programmed timeout period once sequencing is completed and all monitored channels are within their respective thresholds. Up to the boot-up phase, the GPIO_s and EN_OUT_s are high impedance. Apply 2.8V to 14V to VCC to power the MAX16067. Bypass VCC to ground with a 10FF capacitor. Two internal voltage regulators, ABP and DBP, supply power to the analog and digital circuitry within the device. For operation at 3.6V or lower, disable the regulators by connecting ABP and DBP to VCC. ABP is a 3.0V (typ) voltage regulator that powers the internal analog circuitry. Bypass ABP to GND with a 1FF ceramic capacitor installed as close as possible to the device. DBP is an internal 3.0V (typ) voltage regulator. DBP powers flash and digital circuitry. All push-pull outputs refer to DBP. DBP supplies the input voltage to the internal charge pump when the programmable outputs are configured as charge-pump outputs. Bypass the DBP output to GND with a 1FF ceramic capacitor installed as close as possible to the device. Do not power external circuitry from ABP or DBP. To sequence a system of power supplies safely, the output voltage of a power supply must be good before the next power supply may turn on. Connect EN_OUT_ outputs to the enable input of the external power supplies and connect MON_ inputs to the output of the power supplies for voltage monitoring. More than one MON_ can be used if the power supply has multiple outputs. Sequence Order The MAX16067 provides a system of ordered slots to sequence multiple power supplies. To determine the sequence order, assign each EN_OUT_ to a slot ranging from Slot 1 to Slot 6 (Table 6b). EN_OUT_(s) assigned to Slot 1 are turned on first, followed by outputs assigned to Slot 2 through Slot 6. Multiple EN_OUT_s assigned to the same slot turn on at the same time. Each slot includes a built-in configurable sequence delay (registers r77h to r7Dh) ranging from 80Fs to 5.079s. During a reverse sequence, slots are turned off in reverse order starting from Slot 6. The MAX16067 can be configured to power down in simultaneous mode or in reverse-sequence mode as set in r75h[0]. Set r75h[0] to `1' for reverse sequence power-down. See Tables 5 and 6 for the MON_ and EN_OUT_ slot assignment bits, and Tables 2 and 3 for the sequence delays. During power-up or power-down sequencing, the current sequencer state can be found in r21h[3:0].
Power
Sequencing
10
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Table 1. Current Sequencer Slot
REGISTER ADDRESS BIT RANGE Current-sequencer state 0000 = Slot0 0001 = Slot1 0010 = Slot2 0011 = Slot3 0100 = Slot4 0101 = Slot5 0110 = Slot6 0111 = Power-on mode 1000 = Fault state 1001 to 1111 = Unused Reserved DESCRIPTION
MAX16067
21h
[3:0]
[7:4]
A sequencing delay occurs between each slot and is configured in registers 77h-7Dh as shown in Table 2. Each sequencing delay is stored as an 8-bit value and is calculated as follows: t SEQ = 5 x 10 -6 x 2 a x (16 + b) where tSEQ is in seconds, a is the decimal value of the 4 MSBs and b is the decimal value of the 4 LSBs. See Table 3 for example calculations. Enable Input (EN) To initiate sequencing and enable monitoring, the voltage at EN must be above 1.24V (typ) and the software enable bit in r73h[0] must be set to `1.' To power down and disable monitoring, either pull EN below 1.215V (typ) or set the software enable bit to `0.' See Table 4 for the software enable bit configurations. Connect EN to ABP if not used.
(
)
If a fault condition occurs during the power-up cycle, the EN_OUT_ outputs are powered down immediately, regardless of the state of EN. In the monitoring state, if EN falls below the threshold, the sequencing state machine begins the power-down sequence. If EN rises above the threshold during the power-down sequence, the sequence state machine continues the power-down sequence until all the channels are powered off and then the device immediately begins the power-up sequence. When in the monitoring state, and when EN falls below the undervoltage threshold, a register bit, ENRESET (r20h[2]), is set to a `1.' This register bit latches and must be cleared through software. This bit indicates if RESET asserted low due to EN going under the threshold. The POR state of ENRESET is `0'. The bit is only set on a falling edge of the EN comparator output or the software enable bit. If operating in latch-on fault mode, toggle EN or toggle the software enable bit to clear the latch condition and restart the device once the fault condition has been removed.
Table 2. Slot Delay Register
REGISTER ADDRESS 77h 78h 79h 7Ah 7Bh 7Ch 7Dh FLASH ADDRESS 277h 278h 279h 27Ah 27Bh 27Ch 27Dh BIT RANGE [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] DESCRIPTION Sequence slot 0 to slot 1 delay Sequence slot 1 to slot 2 delay Sequence slot 2 to slot 3 delay Sequence slot 3 to slot 4 delay Sequence slot 4 to slot 5 delay Sequence slot 5 to slot 6 delay Sequence slot 6 to power-on state delay
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11
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Table 3. Power-Up/Power-Down Slot Delays
Code 0000 0000 * * * 1111 1111
t SEQ = 5 x 10 -6 x 2 a x (16 + b) = 5 x 10 -6 x 2 0 x (16 + 0) = 80s
* * *
(
)
(
Value
)
t SEQ = 5 x 10 -6 x 2 a x (16 + b) = 5 x 10 -6 x 215 x (16 + 15) = 5.079s
(
)
(
)
Table 4. Software Enable Configurations
REGISTER ADDRESS FLASH ADDRESS BIT RANGE Software enable 1 = Sequencing enabled 0 = Power-down Reserved 1 = Margin mode enabled Reserved Independent watchdog mode enable 1 = Watchdog timer is independent of sequencer 0 = Watchdog timer boots after sequence completes DESCRIPTION
[0] [1] 73h 273h [2] [3] [4]
Monitoring Inputs While Sequencing An enabled MON_ input can be assigned to a slot ranging from Slot 1 to Slot 6. EN_OUT_s are always asserted at the beginning of a slot. The supply voltages connected to the MON_ inputs must exceed the undervoltage threshold before the programmed fault timeout period expires, otherwise, a fault condition occurs. Once a MON_ input crosses the undervoltage threshold, the monitoring for overvoltage begins. The undervoltage and overvoltage threshold checking cannot be disabled during power-up and power-down. See Tables 5 and 6 for the MON_ slot assignment bits. The programmed sequence delay is then counted before moving to the next slot.
Slot 0 does not monitor any MON_ input and does not control any EN_OUT_. Slot 0 waits for the software enable bit r73h[0] to be a logic-high and for the voltage on EN to rise above 1.24V (typ) before initiating the power-up sequence and counting its own sequence delay. Any MON_ input that suffers a fault during power-up sequencing causes all the EN_OUT_s to turn off and the sequencer to shut down regardless of the state of the critical fault enables (see the Faults section). If a MON_ input is less critical to system operation, it can be configured as "monitoring only" (see Table 6a) for sequencing. Monitoring for MON_ inputs assigned as "monitoring only" begins after sequencing is complete, and can trigger a critical fault only if specifically configured to do so using the critical fault enables.
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
SLOT 0 SLOT 1 SLOT 2 SLOT 6
tFAULT SLOT1-SLOT2 DELAY EN_OUT1 BOTH ARE ASSIGNED TO SLOT 1 MON4 UV/OV MONITORING BEGINS WHEN MON4 REACHES UV THRESHOLD EN_OUT2 BOTH ARE ASSIGNED TO SLOT 2 MON3 SLOT1-SLOT2 DELAY OV
UV MON4 MUST REACH UV THRESHOLD BY THIS TIME
RESET TIMEOUT
MON5
RESET
EN
Figure 3. Delay and Reset Timing
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Table 5. MON_ and EN_OUT_ Assignment Registers
REGISTER ADDRESS FLASH ADDRESS BIT RANGE [2:0] 7Eh 27Eh [3] [6:4] [7] [2:0] 7Fh 27Fh [3] [6:4] [7] [2:0] 80h 280h [3] [6:4] [7] 81h-83h 84h 85h 86h 281h-283h 284h 285h 286h -- [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] MON1 Not used MON2 Not used MON3 Not used MON4 Not used MON5 Not used MON6 Not used Not used EN_OUT1 EN_OUT2 EN_OUT3 EN_OUT4 EN_OUT5 EN_OUT6 DESCRIPTION
Table 6a. MON_ Slot Assignment Codes
SLOT ASSIGNMENT CODE 000 001 010 011 100 101 110 111 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Monitoring-only state MON_ DESCRIPTION Not assigned
Table 6b. EN_OUT_ Slot Assignment Codes
SLOT ASSIGNMENT CODE 0000 0001 0010 0011 0100 0101 0110 1101 1110 -- EN_OUT_ DESCRIPTION Not assigned Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 General-purpose input General-purpose output All other unspecified codes are not assigned.
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Power-Up On power-up, when EN is high and the software enable bit is `1', the MAX16067 begins sequencing with Slot 0. After the sequencing delay for Slot 0 expires, the sequencer advances to Slot 1, and all EN_OUT_s assigned to the slot assert. All MON_ inputs assigned to Slot 1 are monitored and when the voltage rises above the undervoltage (UV) fault threshold, the sequence delay counter is started. When the sequence delay expires, the MAX16067 proceeds to the next slot. When the tFAULT counter expires before all MON_ inputs assigned to the slot are above the fault UV threshold, a fault asserts. EN_OUT_ outputs are disabled and the MAX16067 returns to the fault state. Register r75h[4:1] sets the tFAULT delay. See Table 7 for details. After the voltages on all MON_ inputs assigned to the last slot exceed the UV fault threshold and the slot delay expires, the MAX16067 starts the reset timeout counter. After the reset timeout, RESET deasserts. See Table 22 for more information on setting the reset timeout. Power-Down Power-down starts when EN is pulled low or the software enable bit is set to `0.' Power down EN_OUT_s simultaneously or in reverse sequence mode by setting the reverse sequence bit (r75h[0]) appropriately. Set r75h[0] to `1' to power down in reverse sequence. Reverse Sequence Mode When the MAX16067 is fully powered up and EN is pulled low or the software enable bit is set to `0', the EN_OUT_s assigned to Slot 6 deassert, the MAX16067 waits for the Slot 6 sequence delay and then proceeds to the previous slot (Slot 5), and so on until the EN_OUT_s assigned to Slot 1 turn off. When simultaneous powerdown is selected (r75h[0] is set to `0'), all EN_OUT_s turn off at the same time. The MAX16067 features an internal 10-bit ADC that monitors the MON_ voltage inputs. An internal multiplexer cycles through each of the enabled inputs, taking less than 24Fs for a complete monitoring cycle. Each acquisition takes approximately 4Fs. At each multiplexer stop, the 10-bit ADC converts the analog input to a digital result and stores the result in a register. ADC conversion results are stored in registers r00h-r0Bh (see Table 9). Use the SMBus or JTAG serial interface to read ADC conversion results. The MAX16067 provides six inputs, MON1-MON6, for voltage monitoring. Each input-voltage range
Table 7. tFAULT Delay Settings
r75h[4:1] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 FAULT DELAY 120Fs 150Fs 250Fs 380Fs 600Fs 1ms 1.5ms 2.5ms 4ms 6ms 10ms 15ms 25ms 40ms 60ms 100ms
MAX16067
is programmable in registers r43h-r44h (see Table 8). When MON_ configuration registers are set to '11,' MON_ voltages are not monitored and the multiplexer does not stop at these inputs, decreasing the total cycle time. These inputs cannot be configured to trigger fault conditions. The two programmable thresholds for each monitored voltage include an overvoltage and an undervoltage threshold. See the Faults section for more information on setting overvoltage and undervoltage thresholds. All voltage thresholds are 8 bits wide. The 8 MSBs of the 10-bit ADC conversion result are compared to these overvoltage and undervoltage thresholds. For any undervoltage or overvoltage condition to be monitored and any faults detected, the MON_ input must be assigned to a sequence order or set to monitoring mode as described in the Sequencing section. Inputs that are not enabled are not converted by the ADC; they contain the last value acquired before that channel was disabled. The ADC conversion result registers are reset to 00h at boot-up. These registers are not reset when a reboot command is executed. To temporarily disable voltage monitoring during voltage margining conditions, set r73h[2] to `1' to enable margining mode functionality. Faults, except for faults triggered by EXTFAULT pulled low externally, are not recorded when the device is in margining mode but the ADC continues to run and conversion results continue to be available. Set r73h[2] back to `0' for normal functionality.
15
Voltage Monitoring
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Table 8. ADC Configuration Registers
REGISTER ADDRESS FLASH ADDRESS BIT RANGE DESCRIPTION MON1 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted MON2 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted MON3 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted MON4 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted MON5 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted MON6 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted Not used
[1:0]
[3:2] 43h 243h [5:4]
[7:6]
[1:0]
44h
244h [3:2]
[7:4]
Table 9. ADC Conversion Results (Read Only)
REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 16 BIT RANGE [7:0] [7:6] [7:0] [7:6] [7:0] [7:6] [7:0] [7:6] [7:0] [7:6] [7:0] [7:6] MON1 result (MSB) MON1 result (LSB) MON2 result (MSB) MON2 result (LSB) MON3 result (MSB) MON3 result (LSB) MON4 result (MSB) MON4 result (LSB) MON5 result (MSB) MON5 result (LSB) MON6 result (MSB) MON6 result (LSB) DESCRIPTION
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
GPIO1-GPIO6 are programmable general-purpose inputs/outputs. GPIO1-GPIO6 are configurable as a manual reset input, a watchdog timer input and output, logic inputs/outputs, and fault-dependent outputs. When programmed as outputs, GPIOs are open-drain or pushpull. See Tables 10 and 11 for more detailed information on configuring GPIO1-GPIO6.
General-Purpose Inputs/Outputs
When GPIO1-GPIO6 are configured as general-purpose inputs/outputs, read values from the GPIO ports through r1Eh and write values to GPIOs through r3Eh. Note that r3Eh has a corresponding flash register, which programs the default state of a general purpose output. See Table 12 for more information on reading and writing to the GPIO.
MAX16067
Table 10. GPIO_ Configuration Registers
REGISTER ADDRESS FLASH ADDRESS BIT RANGE [1:0] 3Fh 23Fh [3:2] [5:4] [7:6] [1:0] 40h 240h [3:2] [4] [7:5] GPIO1 configuration GPIO2 configuration GPIO3 configuration GPIO4 configuration GPIO5 configuration GPIO6 configuration ARAEN bit Not used DESCRIPTION
Table 11. GPIO_ Function Configuration Bits
GPIO1 00 01 10 11 Logic input Logic output (push-pull) Logic output (open drain) ALERT (open drain) GPIO2 Logic input Logic output (push-pull) Logic output (open drain) FAULT (open drain) GPIO3 Logic input Logic output (push-pull) Logic output (open drain) MR input GPIO4 Logic input Logic output (push-pull) Logic output (open drain) WDI GPIO5 Logic input Logic output (push-pull) Logic output (open drain) WDO (open drain) GPIO6 Logic input Logic output (push-pull) Logic output (open drain) EXTFAULT (open drain)
Table 12. GPIO_ State Registers
REGISTER ADDRESS FLASH ADDRESS BIT RANGE [0] [1] [2] 1Eh -- [3] [4] [5] [7:6] [0] [1] [2] 3Eh 23Eh [3] [4] [5] [7:6] GPIO1 input state GPIO2 input state GPIO3 input state GPIO4 input state GPIO5 input state GPIO6 input state Not used GPIO1 output state GPIO2 output state GPIO3 output state GPIO4 output state GPIO5 output state GPIO6 output state Not used 17 DESCRIPTION
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
ALERT GPIO1 is configurable as the SMBus alert signal, ALERT. ALERT asserts when any fault condition occurs. When the SMBus host sends the ARA (Alert Response Address), the MAX16067 responds with its slave address and deasserts ALERT. ALERT is an open-drain output. Set the ARAEN bit in r40h[4] to `1' to disable the ARA feature. Under these conditions, the device does not respond to an ARA on the SMBus line. FAULT GPIO2 is configurable as a dedicated fault output, FAULT. FAULT asserts when an overvoltage or undervoltage condition occurs on the selected inputs. FAULT dependencies are set using registers r36h and r37h (see Table 13). When FAULT depends on more than one MON_, the fault output asserts when one or more MON_ exceeds a programmed threshold voltage. FAULT acts independently of the critical fault system, described in the Critical Faults section. Use r37h[7] to set the polarity of FAULT. Manual Reset (MR) GPIO3 is configurable to act as an active-low manual reset input, MR. Drive MR low to assert RESET. RESET remains asserted for the selected reset timeout period after MR transitions from low to high. When connecting MR to a pushbutton, use a pullup resistor. See the Reset Output section for more information on selecting a reset timeout period. Watchdog Input (WDI) and Output (WDO) GPIO4 and GPIO5 are configurable as the watchdog timer input (WDI) and output, WDO, respectively. See Table 23 for configuration details. WDO is an open-drain, active-low output. See the Watchdog Timer section for more information about the operation of the watchdog timer. External Fault (EXTFAULT) GPIO6 is configurable as the external fault input/output, EXTFAULT. EXTFAULT asserts if any monitored voltage exceeds an overvoltage or undervoltage threshold. EXTFAULT also asserts if a power-up or power-down sequencing fault occurs. This signal can be used to cascade multiple MAX16067s. Pull EXTFAULT low externally to force the sequencer to enter a fault state. Under these conditions, all outputs deassert. Two configuration bits determine the behavior of the MAX16067 when EXTFAULT is pulled low by an external device. Register bit r72h[5], if set to a `1', causes the sequencer state machine to enter the fault state, deasserting all the outputs when EXTFAULT is pulled low. When this happens, the flag bit r1Ch[6] is set to indicate the cause of the fault. If register bit r6Dh[2] is set in addition to r72h[5], EXTFAULT going low triggers a nonvolatile fault log operation.
Table 13. FAULT Dependencies
REGISTER ADDRESS FLASH ADDRESS BIT RANGE [0] [1] [2] 36h 236h [3] [4] [5] [7:6] [0] [1] [2] [3] 37h 237h [4] [5] [6] [7] DESCRIPTION FAULT depends on MON1 undervoltage threshold FAULT depends on MON2 undervoltage threshold FAULT depends on MON3 undervoltage threshold FAULT depends on MON4 undervoltage threshold FAULT depends on MON5 undervoltage threshold FAULT depends on MON6 undervoltage threshold Not used FAULT depends on MON1 overvoltage threshold FAULT depends on MON2 overvoltage threshold FAULT depends on MON3 overvoltage threshold FAULT depends on MON4 overvoltage threshold FAULT depends on MON5 overvoltage threshold FAULT depends on MON6 overvoltage threshold Not used 0 = FAULT is an active-low digital output 1 = FAULT is an active-high digital output
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
The MAX16067 monitors the input (MON_) channels and compares the results with an overvoltage threshold and an undervoltage threshold. Based on these conditions, the MAX16067 asserts various fault outputs and save specific information about the channel conditions and voltages into the nonvolatile flash. Once a critical fault event occurs, the failing channel condition, ADC conversions at the time of the fault, or both can be saved by configuring the event logger. The event logger records a single failure in the internal flash and sets a lock bit which protects the stored fault data from accidental erasure on a subsequent power-up.
Faults
The MAX16067 is capable of measuring overvoltage and undervoltage fault events. Fault conditions are detected at the end of each ADC conversion. An overvoltage event occurs when the voltage at a monitored input exceeds the overvoltage threshold for that input. An undervoltage event occurs when the voltage at a monitored input falls below the undervoltage threshold. Fault thresholds are set in registers r49h-r59h as shown in Table 14. Disabled inputs are not monitored for fault conditions and are skipped over by the input multiplexer. Only the upper 8 bits of a conversion result are compared with the programmed fault thresholds.
MAX16067
Table 14. Fault Threshold Registers
REGISTER ADDRESS 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h FLASH ADDRESS 248h 249h 24Ah 24Bh 24Ch 24Dh 24Eh 24Fh 250h 251h 252h 253h 254h 255h 256h 257h 258h 259h BIT RANGE [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Not used MON1 overvoltage threshold MON1 undervoltage threshold Not used MON2 overvoltage threshold MON2 undervoltage threshold Not used MON3 overvoltage threshold MON3 undervoltage threshold Not used MON4 overvoltage threshold MON4 undervoltage threshold Not used MON5 overvoltage threshold MON5 undervoltage threshold Not used MON6 overvoltage threshold MON6 undervoltage threshold DESCRIPTION
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Deglitch Fault conditions are detected at the end of each conversion. When the voltage on an input falls outside a monitored threshold for one acquisition, the input multiplexer remains on that channel and performs several successive conversions. To trigger a fault, the input must stay outside the threshold for a certain number of acquisitions as determined by the deglitch setting in r74h[6:5] (see Table 15). Fault Flags Fault flags indicate the fault status of a particular input. The fault flag of any monitored input in the device can be read at any time from registers r1Bh and r1Ch, as shown in Table 16. Clear a fault flag by writing a `1' to the appropriate bit in the flag register. Unlike the fault signals sent to the fault outputs, these bits are masked by the critical fault enable bits (see Table 17). The fault flag is only set when the matching enable bit in the critical fault enable register is also set. If GPIO6 is configured as the EXTFAULT input/output and EXTFAULT is pulled low by an external circuit, bit r1Ch[6] is set. The SMB Alert (ALERT) bit is set if the MAX16067 has asserted the SMBus Alert output. Clear by writing a `1'. See the SMBALERT (ALERT) section for more details.
Table 15. Deglitch Configuration
REGISTER ADDRESS FLASH ADDRESS BIT RANGE DESCRIPTION Voltage comparator deglitch configuration 00 = 2 cycles 01 = 4 cycles 10 = 8 cycles 11 = 16 cycles
74h
274h
[6:5]
Table 16. Fault Flags
REGISTER ADDRESS BIT RANGE [0] [1] [2] 1Bh [3] [4] [5] [7:6] [0] [1] [2] 1Ch [3] [4] [5] [6] [7] MON1 undervoltage threshold MON2 undervoltage threshold MON3 undervoltage threshold MON4 undervoltage threshold MON5 undervoltage threshold MON6 undervoltage threshold Reserved MON1 overvoltage threshold MON2 overvoltage threshold MON3 overvoltage threshold MON4 overvoltage threshold MON5 overvoltage threshold MON6 overvoltage threshold External fault (EXTFAULT) SMB alert DESCRIPTION
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Critical Faults During normal operation, a fault condition can be configured to shut down all the EN_OUT_s and store fault information in the flash memory by setting the appropriate critical fault enable bits. During power-up and power-down, all sequenced MON inputs are considered critical. Faults during power-up and power-down always cause the EN_OUT_s to turn off and can store fault information in the flash memory, depending on the contents of r6Dh[1:0]. Set the appropriate critical fault enable bits in registers r6Eh-r72h (see Table 17) for a fault condition to trigger a critical fault. Logged fault information is stored in flash registers r200h-r208h (see Table 18). After fault information is logged, the flash is locked and must be unlocked to enable a new fault log to be stored. Write a `0' to r8Ch[1] to unlock the configuration flash. Fault information can be configured to store ADC conversion results and/or fault flags in registers. Select the critical fault configuration in r6Dh[1:0]. Set r6Dh[1:0] to `11' to turn off the fault logger. All stored ADC results are 8 bits wide (MSBs of the conversion). Power-Up/Power-Down Faults All EN_OUT_s deassert when an overvoltage or undervoltage fault is detected during power-up/power-down and the MAX16067 enters to the fault state. Fault information can be stored to flash depending on r6D[1:0] (see Table 17).
MAX16067
Table 17. Critical Fault Configuration
REGISTER ADDRESS FLASH ADDRESS BIT RANGE DESCRIPTION Fault Information to Log 00 = Save failed line flags and ADC values in flash 01 = Save only failed line flags in flash 10 = Save only ADC values in flash 11 = Do not save anything 1 = Fault log triggered when EXTFAULT is pulled low externally Not used 1 = Fault log triggered when MON1 is below its undervoltage threshold 1 = Fault log triggered when MON2 is below its undervoltage threshold 1 = Fault log triggered when MON3 is below its undervoltage threshold 1 = Fault log triggered when MON4 is below its undervoltage threshold 1 = Fault log triggered when MON5 is below its undervoltage threshold 1 = Fault log triggered when MON6 is below its undervoltage threshold Not used Not used 1 = Fault log triggered when MON1 is above its overvoltage threshold 1 = Fault log triggered when MON2 is above its overvoltage threshold 1 = Fault log triggered when MON3 is above its overvoltage threshold 1 = Fault log triggered when MON4 is above its overvoltage threshold 1 = Fault log triggered when MON5 is above its overvoltage threshold 1 = Fault log triggered when MON6 is above its overvoltage threshold Not used Not used Not used 1 = EXTFAULT pulled low externally causes sequencer to enter fault state, turning off all EN_OUT_s 0 = EXTFAULT pulled low externally does not cause sequencer to enter fault state Not used
[1:0] 6Dh 26Dh [2] [7:3] [0] [1] [2] 6Eh 26Eh [3] [4] [5] [7:6] [3:0] [4] 6Fh 26Fh [5] [6] [7] [0] 70h 71h 270h 271h [1] [7:2] [7:0] [4:0] 72h 272h [5] [7:6]
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Table 18. Nonvolatile Fault Log Registers
FLASH ADDRESS BIT RANGE DESCRIPTION Sequencer state where the fault has happened (see Table 1 for state codes). Fault has happened during power-up if bit [3] = 0 and during power-down if [3] = 1. Bits [2:0] indicate the slot number. Not used Fault log triggered on MON1 falling below its undervoltage threshold Fault log triggered on MON2 falling below its undervoltage threshold Fault log triggered on MON3 falling below its undervoltage threshold Fault log triggered on MON4 falling below its undervoltage threshold Fault log triggered on MON5 falling below its undervoltage threshold Fault log triggered on MON6 falling below its undervoltage threshold Not used Fault log triggered on MON1 exceeding its overvoltage threshold Fault log triggered on MON2 exceeding its overvoltage threshold Fault log triggered on MON3 exceeding its overvoltage threshold Fault log triggered on MON4 exceeding its overvoltage threshold Fault log triggered on MON5 exceeding its overvoltage threshold Fault log triggered on MON6 exceeding its overvoltage threshold Fault log triggered on EXTFAULT Not used MON1 ADC output (8 MSBs) MON2 ADC output (8 MSBs) MON3 ADC output (8 MSBs) MON4 ADC output (8 MSBs) MON5 ADC output (8 MSBs) MON6 ADC output (8 MSBs)
200h
[3:0] [7:4] [0] [1] [2]
201h
[3] [4] [5] [7:6] [0] [1] [2] [3] [4] [5] [6] [7]
202h
203h 204h 205h 206h 207h 208h
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Autoretry/Latch Mode The MAX16067 can be configured for one of two fault management methods: autoretry or latch-on-fault. Set r74h[4:3] to `00' to select the latch-on-fault mode. In this configuration, EN_OUT_s deassert after a critical fault event. The device does not reinitiate the power-up sequence until EN is toggled or the software enable bit is toggled. See the Enable Input (EN) section for more information on setting the software enable bit. Set r74h[4:3] to a value other than `00' to select autoretry mode (see Table 19). In this configuration, the device shuts down after a critical fault event then restarts following a configurable delay. Use r74h[2:0] to select an
autoretry delay from 20ms to 1.6s. See Table 19 for more information on setting the autoretry delay. When fault information is stored in flash (see the Critical Faults section) and autoretry mode is selected, set an autoretry delay greater than the time required for the storing operation. When fault information is stored in flash and latch-on-fault mode is chosen, toggle EN or reset the software enable bit only after the completion of the storing operation. When saving information about the failed lines only, ensure a delay of at least 12ms before the restart procedure. Otherwise, ensure a minimum 153ms timeout, to ensure that ADC conversions are completed and values are stored correctly in flash.
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Table 19. Autoretry Configuration
REGISTER ADDRESS FLASH ADDRESS BIT RANGE Retry Delay 000 = 20ms 001 = 40ms 010 = 80ms 011 = 150ms 100 = 280ms 101 = 540ms 110 = 1s 111 = 2s Autoretry/Latch Mode 00 = Latch 01 = Reserved 10 = Reserved 11 = Always retry DESCRIPTION
MAX16067
[2:0] 74h 274h
[4:3]
The MAX16067 includes six programmable outputs. These outputs are capable of connecting to either the enable (EN) inputs of a DC-DC or LDO power supply, or to drive the gate of an n-channel MOSFET in charge-pump mode. Selectable output configurations include: active-low or active-high, open-drain or pushpull. EN_OUT1-EN_OUT3 can act as charge-pump outputs, EN_OUT1-EN_OUT6 can be configured as general-purpose inputs or general-purpose outputs. Use the registers r30h-r33h to configure outputs. See Table 20 for detailed information on configuring EN_OUT1- EN_OUT6.
Programmable Outputs (EN_OUT1-EN_OUT6)
In charge-pump configuration: EN_OUT1, EN_OUT2, and EN_OUT3 act as high-voltage charge-pump outputs to drive up to three external n-channel MOSFETs. During sequencing, an EN_OUT_ output is configured as a charge-pump output 11V above GND. See the Sequencing section for more detailed information on power-supply sequencing. In open-drain output configuration: Connect an external pullup resistor from the output to an external voltage up to 5.5V (EN_OUT4, EN_OUT5, EN_OUT6) or 14V (EN_OUT1, EN_OUT2, EN_OUT3) when configured as an open-drain output. Choose the pullup resistor depending on the number of devices connected to the open-drain output and the allowable current consumption. The open-drain output configuration allows wiredOR connection. In push-pull configuration: The MAX16067's programmable outputs are referenced to VDBP.
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Table 20. EN_OUT1-EN_OUT6 Configuration
REGISTER ADDRESS FLASH ADDRESS BIT RANGE EN_OUT1 Configuration 00 = Active-low, open drain 01 = Active-high, open drain 10 = Active-low, push-pull 11 = Active-high, push-pull EN_OUT2 Configuration 00 = Active-low, open drain 01 = Active-high, open drain 10 = Active-low, push-pull 11 = Active-high, push-pull EN_OUT3 Configuration 00 = Active-low, open drain 01 = Active-high, open drain 10 = Active-low, push-pull 11 = Active-high, push-pull EN_OUT4 Configuration 00 = Active-low, open drain 01 = Active-high, open drain 10 = Active-low, push-pull 11 = Active-high, push-pull EN_OUT5 Configuration 00 = Active-low, open drain 01 = Active-high, open drain 10 = Active-low, push-pull 11 = Active-high, push-pull EN_OUT6 Configuration 00 = Active-low, open drain 01 = Active-high, open drain 10 = Active-low, push-pull 11 = Active-high, push-pull Not used EN_OUT1 Charge-Pump Output Configuration 0 = Charge-pump output disabled 1 = Charge-pump output enabled (active-high) EN_OUT2 Charge-Pump Output Configuration 0 = Charge-pump output disabled 1 = Charge-pump output enabled (active-high) EN_OUT3 Charge-Pump Output Configuration 0 = Charge-pump output disabled 1 = Charge-pump output enabled (active-high) Not used DESCRIPTION
[1:0]
[3:2] 30h 230h [5:4]
[7:6]
[1:0]
31h
231h [3:2]
[7:4] [0]
33h
233h
[1]
[2] [7:3]
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
EN_OUT_s as GPIO EN_OUT1-EN_OUT6 can be configured as general-purpose inputs by setting the sequencing slot assignments in r84h-r86h to `1101' or as general-purpose outputs by setting the slot assignments to `1110'. See Tables 5 and 6. If an EN_OUT_ is configured as a general-purpose input, the state of the GPIO can be read from r1Fh (see Table 21). If an EN_OUT_ is configured as a generalpurpose output, it is controlled by r34h. EN_OUT_ State During Power-Up When VCC is ramped from 0V to the operating supply voltage, the EN_OUT_ output is high impedance until VCC reaches UVLO and then EN_OUT_ goes into the configured deasserted state. See Figures 4 and 5. Configure RESET as an active-low push-pull or opendrain output pulled up to VCC through a 10kI resistor for Figures 4 and 5.
MAX16067
Table 21. EN_OUT_ GPIO State Registers
REGISTER ADDRESS FLASH ADDRESS BIT RANGE [0] [1] [2] 1Fh -- [3] [4] [5] [7:6] [0] [1] [2] 34h 234h [3] [4] [5] [7:6] EN_OUT1 input state EN_OUT2 input state EN_OUT3 input state EN_OUT4 input state EN_OUT5 input state EN_OUT6 input state Not used 1 = Assert EN_OUT1 1 = Assert EN_OUT2 1 = Assert EN_OUT3 1 = Assert EN_OUT4 1 = Assert EN_OUT5 1 = Assert EN_OUT6 Not used DESCRIPTION
MAX16067 fig04
MAX16067 fig05
VCC 2V/div 0V
RESET 2V/div 0V EN_OUT_ 2V/div 0V 20ms/div
UVLO
VCC 2V/div 0V RESET 2V/div 0V
ASSERTED LOW HIGH-Z 10ms/div
EN_OUT_ 2V/div 0V
Figure 4. RESET and EN_OUT_ During Power-Up, EN_OUT_ is in Open-Drain Active-Low Configuration
Figure 5. RESET and EN_OUT_ During Power-Up, EN_OUT_ is in Push-Pull Active-High Configuration
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
The reset output, RESET, indicates the status of the sequencer and the monitored inputs. It asserts during power-up/power-down and deasserts following the reset timeout period once the power-up sequence is complete. The power-up sequence is complete when any MON_ inputs assigned to slot 6 exceed the undervoltage thresholds and the slot 6 sequence delay expires. When no MON_ inputs are assigned to slot 6, the power-up sequence is complete after the slot sequence delay expires. During normal monitoring, RESET can be configured to assert when any combination of MON_ inputs violates configurable combinations of undervoltage or overvoltage
Reset Output
thresholds. Select the combination of MON_ inputs using r3Ch[5:0] and r3Dh[5:0]. Note that MON_ inputs configured as critical faults always cause RESET to assert regardless of these configuration bits. RESET can be configured as push-pull or open drain using r3Bh[3], and active high or active low using r3Bh[2]. Select the reset timeout by loading a value from Table 22 into r3Bh[7:4]. To generate a one-shot pulse on RESET, write a `1' into r3Bh[0]. The pulse width is the configured reset timeout. Register bit r3Bh[0] clears automatically (see Table 22). The current state of RESET can be checked by reading r20h[0].
Table 22. Reset Output Configuration
REGISTER ADDRESS FLASH ADDRESS BIT RANGE RESET Soft Trigger 0 = Normal RESET behavior 1 = Force RESET to assert Not used 0 = Active low 1 = Active high 0 = Open drain 1 = Push-pull Reset Timeout Period 0000 = 25Fs 0001 = 1.5ms 0010 = 2.5ms 0011 = 4ms 0100 = 6ms 0101 = 10ms 0110 = 15ms 0111 = 25ms 1000 = 40ms 1001 = 60ms 1010 = 100ms 1011 = 150ms 1100 = 250ms 1101 = 400ms 1110 = 600ms 1111 = 1s DESCRIPTION
[0] [1] [2] [3]
3Bh
23Bh
[7:4]
26
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Table 22. Reset Output Configuration (continued)
REGISTER ADDRESS FLASH ADDRESS BIT RANGE [0] [1] [2] 3Ch 23Ch [3] [4] [5] [7:6] [0] [1] [2] 3Dh 23Dh [3] [4] [5] [7:6] DESCRIPTION 1 = RESET depends on MON1 undervoltage 1 = RESET depends on MON2 undervoltage 1 = RESET depends on MON3 undervoltage 1 = RESET depends on MON4 undervoltage 1 = RESET depends on MON5 undervoltage 1 = RESET depends on MON6 undervoltage Not used 1 = RESET depends on MON1 overvoltage 1 = RESET depends on MON2 overvoltage 1 = RESET depends on MON3 overvoltage 1 = RESET depends on MON4 overvoltage 1 = RESET depends on MON5 overvoltage 1 = RESET depends on MON6 overvoltage Not used
MAX16067
The watchdog timer operates together with or independently of the MAX16067. When operating in dependent mode, the watchdog is not activated until the sequencing is complete and RESET is deasserted. When operating in independent mode, the watchdog timer is independent of the sequencing operation and activates immediately after VCC exceeds the UVLO threshold and the boot phase is complete. Set r73h[4] to `0' to configure the watchdog in dependent mode. Set r73h[4] to `1' to configure the watchdog in independent mode. See Table 23 for more information on configuring the watchdog timer in dependent or independent mode. The watchdog timer can be reset by toggling the WDI input (GPIO4) or by writing a `1' to r75h[5]. Dependent Watchdog Timer Operation Use the watchdog timer to monitor FP activity in two modes. Flexible timeout architecture provides an adjustable watchdog startup delay of up to 300s, allowing complicated systems to complete lengthy boot-up routines. An adjustable watchdog timeout allows the supervisor to provide quick alerts when the processor activity fails. After each reset event (VCC drops below UVLO then returns above UVLO, software reboot, manual reset (MR), EN input going low then high, or watchdog reset) and once sequencing is complete, the watchdog startup delay provides an extended time for the system to power
Watchdog Timer
up and fully initialize all FP and system components before assuming responsibility for routine watchdog updates. Set r76h[6:4] to a value other than `000' to enable the watchdog startup delay. Set r76h[6:4] to `000' to disable the watchdog startup delay. The normal watchdog timeout period, tWDI, begins after the first transition on WDI before the conclusion of the long startup watchdog period, tWDI_STARTUP (Figures 6 and 7). During the normal operating mode, WDO asserts if the FP does not toggle WDI with a valid transition (highto-low or low-to-high) within the standard timeout period, tWDI. WDO remains asserted until WDI is toggled or RESET is asserted (Figure 7). While EN is low, the watchdog timer is in reset. The watchdog timer does not begin counting until the poweron mode is reached and RESET is deasserted. The watchdog timer is reset and WDO deasserts any time RESET is asserted (Figure 8). The watchdog timer is held in reset while RESET is asserted. The watchdog can be configured to control the RESET output as well as the WDO output. RESET asserts for the reset timeout, tRP, when the watchdog timer expires and the Watchdog Reset Output Enable bit (r76h[7]) is set to `1'. When RESET is asserted, the watchdog timer is cleared and WDO is deasserted, therefore, WDO pulses low for a short time (approximately 1Fs) when
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27
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
the watchdog timer expires. RESET is not affected by the watchdog timer when the Watchdog Reset Output Enable bit (r76h[7]) is set to `0'. If a RESET is asserted by the watchdog timeout, the WDRESET bit is set to `1'. A connected processor can check this bit to see the reset was due to a watchdog timeout. See Table 23 for more information on configuring watchdog functionality. Independent Watchdog Timer Operation When r73h[3] is `1,' the watchdog timer operates in the independent mode. In the independent mode, the watchdog timer operates as if it were a separate device. The watchdog timer is activated immediately upon VCC exceeding UVLO and once the boot-up sequence is finished. When RESET is asserted by the sequencer state machine, the watchdog timer and WDO are not affected. There is a startup delay if r76h[6:4] is set to a value different than `000'. If r76h[6:4] is set to `000', there is not a startup delay. See Table 23 for delay times. In independent mode, if the Watchdog Reset Output Enable bit r76h[7] is set to `1,' when the watchdog timer expires, WDO asserts then RESET asserts. WDO is then deasserts. WDO is low for approximately 1Fs. If the Watchdog Reset Output Enable bit (r76h[7]) is set to `0,' when the watchdog timer expires, WDO asserts but RESET is not affected.
VTH LAST MON_ < tWDI
WDI
tWDI_STARTUP < tWDI
tRP RESET
Figure 6. Normal Watchdog Startup Sequence
VCC WDI 0V tWDI VCC WDO 0V < tWDI < tWDI < tWDI > tWDI < tWDI < tWDI < tWDI
Figure 7. Watchdog Timer Operation
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
VCC WDI 0V VCC RESET 0V VCC WDO 0V 1s < tWDI tWDI tRP < tWDI_STARTUP < tWDI
Figure 8. Watchdog Startup Sequence with Watchdog Reset Enable Bit Set to `1'
Table 23. Watchdog Configuration
REGISTER ADDRESS 73h FLASH ADDRESS 273h BIT RANGE [4] [7] 1 = Independent mode 0 = Dependent mode 1 = Watchdog reset output enabled 0 = Watchdog reset output disabled Watchdog Startup Delay 000 = No initial timeout 001 = 30s 010 = 40s 011 = 80s 100 = 120s 101 = 160s 110 = 220s 111 = 300s Watchdog Timeout 0000 = Watchdog disabled 0001 = 1ms 0010 = 2ms 0011 = 4ms 0100 = 8ms 0101 = 14ms 0110 = 27ms 0111 = 50ms 1000 = 100ms 1001 = 200ms 1010 = 400ms 1011 = 750ms 1100 = 1.4s 1101 = 2.7s 1110 = 5s 1111 = 10s DESCRIPTION
[6:4]
76h
276h
[3:0]
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29
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Register r8Ah provides storage space for a user-defined configuration or firmware version number. Note that this register controls the contents of the JTAG USERCODE register bits 7-0. The user-defined register is stored at r28Ah in the flash memory. Register r8Ch contains the lock bits for the configuration registers, configuration flash, user flash, and fault register lock. See Table 24 for details.
User-Defined Register
Memory Lock Bits
(S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is an open-drain input/ output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7kI for most applications. Bit Transfer Each clock pulse transfers one data bit. The data on SDA must remain stable while SCL is high (Figure 9); otherwise, the MAX16067 registers a START or STOP condition (Figure 10) from the master. SDA and SCL idle high when the bus is not busy. START and STOP Conditions Both SCL and SDA idle high when the bus is not busy. A master device signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. The master device issues a STOP condition by transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a REPEATED START condition is generated, such as in the block read protocol (see Figure 1, SMBus Timing Diagram). Early STOP Conditions The MAX16067 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition. This condition is not a legal SMBus format; at least one clock pulse must separate any START and STOP condition.
The MAX16067 features an SMBus-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX16067 and the master device at clock rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX16067 is a transmit/receive, slave-only device, relying upon a master device to generate a clock signal. The master device (typically a microcontroller) initiates a data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX16067 by transmitting the proper address followed by command and/or data words. The slave address input, A0, is capable of detecting four different states, allowing multiple identical devices to share the same serial bus. The slave address is described further in the Slave Address section. Each transmit sequence is framed by a START
SMBus-Compatible Interface
Table 24. Memory Lock Bits
REGISTER ADDRESS FLASH ADDRESS BIT RANGE Configuration Register Lock 1 = Locked 0 = Unlocked Flash Fault Register Lock 1 = Locked 0 = Unlocked Flash Configuration Lock 1 = Locked 0 = Unlocked User Flash Lock 1 = Locked 0 = Unlocked Not used DESCRIPTION
[0]
[1] 8Ch 28Ch [2]
[3] [7.4]
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
SDA SDA
SCL SCL S P
DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID
START CONDITION
STOP CONDITION
Figure 9. Bit Transfer
Figure 10. START and STOP Conditions
CLOCK PULSE FOR ACKNOWLEDGE
SCL
1
2
8
9
SDA BY TRANSMITTER
S SDA BY RECEIVER
NACK
ACK
Figure 11. Acknowledge
REPEATED START Conditions A REPEATED START can be sent instead of a STOP condition to maintain control of the bus during a read operation. The START and REPEATED START conditions are functionally identical. Acknowledge The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. The receiving device always generates an ACK. The MAX16067 generates an ACK when receiving an address or data by pulling SDA low during the 9th clock period (Figure 11). When transmitting data,
such as when the master device reads data back from the MAX16067, the device waits for the master device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master can reattempt communication at a later time. The MAX16067 generates a NACK after the command byte received during a software reboot, while writing to the flash, or when receiving an illegal memory address.
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Slave Address Use the slave address input, A0, to allow multiple identical devices to share the same serial bus. Connect A0 to GND, DBP (or an external supply voltage greater than 2V), SCL, or SDA to set the device address on the bus. See Table 26 for a listing of all possible 7-bit addresses. The slave address can also be set to a custom value by loading the address into register r8Bh[6:0]. See Table 25. If r8Bh[6:0] is loaded with 00h, the address is set by input A0. Do not set the address to 09h or 7Fh to avoid address conflicts. The slave address setting takes effect immediately after writing to the register. Packet Error Checking (PEC) The MAX16067 features a packet-error checking (PEC) mode that is useful to improve the reliability of the communication bus by detecting bit errors. By enabling PEC, an extra CRC-8 error check byte is added in the data string during each read and/or write sequence. Enable PEC by writing a `1' to r8Bh[7]. The CRC-8 byte is calculated using the polynomial C = X8 + X2 + X + 1 The PEC calculation includes all bytes in the transmission, including address, command and data. The PEC calculation does not include ACK, NACK, START, STOP, or REPEATED START. Command Codes The MAX16067 uses eight command codes for block read, block write, and other commands. See Table 27 for a list of command codes. To initiate a software reboot, send A7h using the send byte format. A software-initiated reboot is functionally the same as a hardware-initiated power-on reset. During boot-up, flash configuration data in the range of 230h-28Ch is copied to r30h-r8Ch registers in the default page. Send command code A8h to trigger a fault store to flash. Configure the Critical Fault Log Control register (6Dh) to store ADC conversion results and/or fault flags. While in the flash page, send command code A9h to access the flash page (addresses from 200h-2FFh). Once command code A9h has been sent, all addresses are recognized as flash addresses only. Send command code AAh to return to the default page (addresses from 000h-0FFh). Send command code ABh to access the user flash-page (addresses from 300h-3FFh), and send command code ACh to return to the flash page.
Table 25. SMBus Settings Register
REGISTER ADDRESS 8Bh FLASH ADDRESS 28Bh BIT RANGE [6:0] [7] DESCRIPTION SMBus Slave Address Register. Set to 00h to use A0 pin address setting. 1= Enable PEC (Packet Error Check).
Table 26. Setting the SMBus Slave Address
SLAVE ADDRESSES A0 0 1 SCL SDA R = Read/write select bit. SLAVE ADDRESS 1010 100R 1010 101R 1010 110R 1010 111R
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Table 27. Command Codes
COMMAND CODE A5h A6h A7h A8h A9h AAh ABh ACh Block write Block read Reboot flash in register file Trigger emergency save to flash Flash page access ON Flash page access OFF User flash access ON (must be in flash page already) User flash access OFF (return to flash page) ACTION
MAX16067
Restrictions When Writing to Flash Flash must be written to 8 bytes at a time. The initial address must be aligned to 8-byte boundaries--the 3 LSBs of the initial address must be `000'. Write the 8 bytes using a single block write command or using eight successive Write Byte commands. A write operation requires 122ms for each 8-byte block. After programming a block, check r20h[1] (see Table 31) to make sure the write operation is complete before attempting to write the next block. Send Byte The send byte protocol allows the master device to send one byte of data to the slave device (see Figure 12). The send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of an ACK if the master tries to send a memory address or command code that is not allowed. If the master sends A5h or A6h, the data is ACK, because this could be the start of the write block or read block. If the master sends a STOP condition before the slave asserts an ACK, the internal address pointer does not change. If the master sends A7h, this signifies a software reboot. The send byte procedure is as follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit memory address or command code. 5) The addressed slave asserts an ACK (or NACK) on SDA. 6) The master sends a STOP condition.
Receive Byte The receive byte protocol allows the master device to read the register content of the MAX16067 (see Figure 12). The flash or register address must be preset with a send byte or write word protocol first. Once the read is complete, the internal pointer increases by one. Repeating the receive byte protocol reads the contents of the next address. The receive byte procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a read bit (high). 3) The addressed slave asserts an ACK on SDA. 4) The slave sends 8 data bits. 5) The master asserts a NACK on SDA. 6) The master generates a STOP condition. Write Byte The write byte protocol (see Figure 12) allows the master device to write a single byte in the default page, extended page, or flash page, depending on which page is currently selected. The write byte procedure is as follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit memory address. 5) The addressed slave asserts an ACK on SDA. 6) The master sends an 8-bit data byte. 7) The addressed slave asserts an ACK on SDA. 8) The master sends a STOP condition.
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
To write a single byte, only the 8-bit memory address and a single 8-bit data byte are sent. The data byte is written to the addressed location if the memory address is valid. The slave asserts a NACK at step 5 if the memory address is not valid. When PEC is enabled, the write byte protocol becomes: 1) 2) 3) 4) 5) 6) 7) 8) 9) The master sends a START condition. The master sends the 7-bit slave ID plus a write bit (low). The addressed slave asserts an ACK on the data line. The master sends an 8-bit command code. The active slave asserts an ACK on the data line. The master sends an 8-bit data byte. The slave asserts an ACK on the data line. The master sends an 8-bit PEC byte. The slave asserts an ACK on the data line (if PEC is good, otherwise NACK). When PEC is enabled, the read byte protocol becomes: 1) 2) 3) 4) 5) 6) 7) 8) 9) The master sends a START condition. The master sends the 7-bit slave ID plus a write bit (low). The addressed slave asserts an ACK on the data line. The master sends 8 data bits. The active slave asserts an ACK on the data line. The master sends a REPEATED START condition. The master sends the 7-bit slave ID plus a read bit (high). The addressed slave asserts an ACK on the data line. The slave sends 8 data bits.
10) The master asserts an ACK on the data line. 11) The slave sends an 8-bit PEC byte. 12) The master asserts a NACK on the data line. 13) The master generates a STOP condition. Block Write The block write protocol (see Figure 12) allows the master device to write a block of data (1-16 bytes) to memory. Preload the destination address by a previous send byte command; otherwise the block write command begins to write at the current address pointer. After the last byte is written, the address pointer remains preset to the next valid address. If the number of bytes to be written causes the address pointer to exceed 8Fh for configuration registers or configuration flash or FFh for user flash, the address pointer stays at 8Fh or FFh, respectively, overwriting this memory address with the remaining bytes of data. The slave generates a NACK at step 5 if the command code is invalid or if the device is busy, and the address pointer is not altered. The block write procedure is as follows: 1 2 3) 4) 5) The master sends a START condition. The master sends the 7-bit slave address and a write bit (low). The addressed slave asserts an ACK on SDA. The master sends the 8-bit command code for block write (94h). The addressed slave asserts an ACK on SDA.
10) The master generates a STOP condition. Read Byte The read byte protocol (see Figure 12) allows the master device to read a single byte located in the default page, extended page, or flash page depending on which page is currently selected. The read byte procedure is as follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit memory address. 5) The addressed slave asserts an ACK on SDA. 6) The master sends a REPEATED START condition. 7) The master sends the 7-bit slave address and a read bit (high). 8) The addressed slave asserts an ACK on SDA. 9) The slave sends an 8-bit data byte. 10) The master asserts a NACK on SDA. 11) The master sends a STOP condition. If the memory address is not valid, it is NACKed by the slave at step 5 and the address pointer is not modified.
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
6) 7) 8) 9) The master sends the 8-bit byte count (1 byte to 16 bytes), n. The addressed slave asserts an ACK on SDA. The master sends 8 bits of data. The addressed slave asserts an ACK on SDA. 5) 6) 7) 8) 9) 3) 4) The addressed slave asserts an ACK on SDA. The master sends 8 bits of the block read command (95h). The slave asserts an ACK on SDA, unless busy. The master generates a REPEATED START condition. The master sends the 7-bit slave address and a read bit (high). The slave asserts an ACK on SDA. The slave sends the 8-bit byte count (16).
MAX16067
10) Repeat steps 8 and 9 n - 1 times. 11) The master sends a STOP condition. When PEC is enabled, the block write protocol becomes: 1) The master sends a START condition. 2) The master sends the 7-bit slave ID plus a write bit (low). 3) The addressed slave asserts an ACK on the data line. 4) The master sends 8 bits of the block write command code. 5) The slave asserts an ACK on the data line. 6) The master sends 8 bits byte count (min 1, max 16) n. 7) The slave asserts an ACK on the data line. 8) The master sends 8 bits of data. 9) The slave asserts an ACK on the data line. 10) Repeat 8 and 9 n - 1 times. 11) The master sends an 8-bit PEC byte. 12) The slave asserts an ACK on the data line (if PEC is good, otherwise NACK). 13) The master generates a STOP condition. Block Read The block read protocol (see Figure 12) allows the master device to read a block of up to 16 bytes from memory. Read fewer than 16 bytes of data by issuing an early STOP condition from the master, or by generating a NACK with the master. The destination address should be preloaded by a previous send byte command; otherwise, the block read command begins to read at the current address pointer. If the number of bytes to be read causes the address pointer to exceed 8Fh for the configuration register or configuration flash or FFh in user flash, the address pointer stays at 8Fh or FFh, respectively. The block read procedure is the following: 1) 2) The master sends a START condition. The master sends the 7-bit slave address and a write bit (low).
10) The master asserts an ACK on SDA. 11) The slave sends 8 bits of data. 12) The master asserts an ACK on SDA. 13) Repeat steps 11 and 12 up to fifteen times. 14) The master asserts a NACK on SDA. 15) The master sends a STOP condition. When PEC is enabled, the block read protocol becomes: 1) The master sends a START condition. 2) The master sends the 7-bit slave ID plus a write bit (low). 3) The addressed slave asserts an ACK on the data line. 4 The master sends 8 bits of the block read command code.
5) The slave asserts an ACK on the data line unless busy. 6) The master sends a REPEATED START condition. 7) The master sends the 7-bit slave ID plus a read bit (high). 8) The slave asserts an ACK on the data line. 9) The slave sends 8-bit byte count (16). 10) The master asserts an ACK on the data line. 11) The slave sends 8 bits of data. 12) The master asserts an ACK on the data line. 13) Repeat 11 and 12 up to 15 times. 14) The slave sends an 8-bit PEC byte. 15) The master asserts a NACK on the data line. 16) The master generates a STOP condition.
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35
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
SEND BYTE FORMAT S ADDRESS 7 BITS R/W ACK 0 0 COMMAND 8 BITS ACK 0 P RECEIVE BYTE FORMAT S ADDRESS 7 BITS R/W ACK 1 0 DATA 8 BITS NACK 1 P
SLAVE ADDRESS: Address DATA BYTE: Presets the internal of the slave on the serial address pointer or represents interface bus. a command. WRITE BYTE FORMAT S ADDRESS 7 BITS R/W ACK 0 0 COMMAND 8 BITS ACK 0 DATA 8 BITS ACK 0 P
SLAVE ADDRESS: Address DATA BYTE: Data is read from of the slave on the serial the location pointed to by the interface bus. internal address pointer. SMBALERT# S ADDRESS 0001100 R/W ACK D.C. 0 DATA 8 BITS NACK 1 P
SLAVE ADDRESS: Address COMMAND BYTE: of the slave on the serial Sets the internal interface bus. address pointer. READ BYTE FORMAT S SLAVE ADDRESS 7 BITS R/W ACK 0 0 COMMAND 8 BITS ACK 0
DATA BYTE: Data is written to the locations set by the internal address pointer. SR SLAVE ADDRESS 7 BITS R/W ACK 1 0
ALERT RESPONSE ADDRESS: SLAVE ADDRESS: Slave places Only the device that its own address on the interrupted the master serial bus. responds to this address. DATA BYTE NACK 8 BITS 1 P
SLAVE ADDRESS: Address COMMAND BYTE: of the slave on the serial Sets the internal interface bus. address pointer. BLOCK WRITE FORMAT S ADDRESS 7 BITS R/W ACK 0 0 COMMAND 8 BITS ACK 0 BYTE COUNT = N 8 BITS
DATA BYTE: Data is written to the locations set by the internal address pointer.
ACK DATA BYTE 1 ACK DATA BYTE ... ACK DATA BYTE N ACK 0 8 BITS 0 8 BITS 0 8 BITS 0
P
SLAVE TO MASTER MASTER TO SLAVE
SLAVE ADDRESS: Address COMMAND BYTE: of the slave on the FAh serial interface bus. BLOCK READ FORMAT S ADDRESS 7 BITS R/W ACK 0 0 COMMAND 8 BITS ACK 0 SR ADDRESS 7 BITS
DATA BYTE: Data is written to the locations set by the internal address pointer.
R/W ACK 1 0
BYTE COUNT = N 8 BITS
ACK DATA BYTE N ACK DATA BYTE ... ACK DATA BYTE N NACK 0 8 BITS 0 8 BITS 0 8 BITS 1
P
SLAVE ADDRESS: Address COMMAND BYTE: of the slave on the FBh serial interface bus. WRITE BYTE FORMAT WITH PEC S ADDRESS 7 BITS R/W ACK 0 0 COMMAND 8 BITS ACK 0
SLAVE ADDRESS: Address DATA BYTE: Data is read from the locations of the slave on the set by the internal address pointer. serial interface bus.
DATA 8 BITS
ACK 0
PEC 8 BITS
ACK 0
P
READ BYTE FORMAT WITH PEC S ADDRESS 7 BITS R/W ACK 0 0 COMMAND 8 BITS ACK SR 0 ADDRESS 7 BITS R/W ACK 1 0 DATA 8 BITS ACK 0 PEC 8 BITS NACK P 1
BLOCK WRITE WITH PEC S ADDRESS 7 BITS R/W ACK 0 0 COMMAND 8 BITS ACK BYTE COUNT N ACK DATA BYTE 1 ACK 0 8 BITS 0 8 BITS 0 DATA BYTE ACK 8 BITS 0 DATA N 8 BITS ACK 0 PEC 8 BITS ACK 0 P
BLOCK READ WITH PEC S ADDRESS 7 BITS R/W ACK 0 0 COMMAND 8 BITS ACK SR 0 ADDRESS 7 BITS R/W ACK BYTE COUNT N ACK DATA BYTE 1 ACK 1 0 8 BITS 0 8 BITS 0 DATA BYTE 8 BITS ACK 0 DATA N 8 BITS ACK 0 PEC 8 BITS NACK 1 P
S = START CONDITION P = STOP CONDITION Sr = REPEATED START CONDITION D.C. = DON'T CARE
ACK = ACKNOWLEDGE, SDA PULLED LOW DURING RISING EDGE OF SCL. NACK = NOT ACKNOWLEDGE, SDA LEFT HIGH DURING RISING EDGE OF SCL. ALL DATA IS CLOCKED IN/OUT OF THE DEVICE ON RISING EDGES OF SCL.
= SDA TRANSITIONS FROM HIGH TO LOW DURING PERIOD OF SCL. = SDA TRANSITIONS FROM LOW TO HIGH DURING PERIOD OF SCL.
Figure 12. SMBus Protocols 36 _____________________________________________________________________________________
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
The MAX16067 supports the SMBus alert protocol. To enable the SMBus alert output, set r40h[4] to `1', then configure GPIO1 to act as the SMBus alert (ALERT) according to Table 11. This output is open drain and uses the wired-OR configuration with other devices on the SMBus. During a fault, the MAX16067 asserts ALERT low, signaling the master that an interrupt has occurred. The master responds by sending the ARA (Alert Response Address) protocol on the SMBus. This protocol is a read byte with 09h as the slave address. The slave acknowledges the ARA (09h) address and sends its own SMBus address to the master. The slave then deasserts ALERT. The master can then query the slave and determine the cause of the fault. By checking r1C[7], the master can confirm that the MAX16067 trig-
SMBALERT (ALERT)
gered the SMBus alert. The master must send the ARA before clearing r1Ch[7]. Clear r1Ch[7] by writing a `1'. If GPIO1 is configured as the SMBus alert output but the SMBus alert feature is disabled (r40h[4] is set to `0'), GPIO1 acts as an additional fault output. The MAX16067 features a JTAG port that complies with a subset of the IEEE 1149.1 specification. Either the SMBus or the JTAG interface can be used to access internal memory; however, only one interface is allowed to run at a time. The MAX16067 contains extra JTAG instructions and registers not included in the JTAG specification that provide access to internal memory. The extra instructions include LOAD ADDRESS, WRITE, READ, REBOOT, and SAVE.
MAX16067
JTAG Serial Interface
REGISTERS AND EEPROM
01100 01011 01010 01001 01000 00111
MEMORY WRITE REGISTER [LENGTH = 8 BITS] MEMORY READ REGISTER [LENGTH = 8 BITS] MEMORY ADDRESS REGISTER [LENGTH = 8 BITS] USER CODE REGISTER [LENGTH = 32 BITS] IDENTIFICATION REGISTER [LENGTH = 32 BITS] BYPASS REGISTER [LENGTH = 1 BIT]
00110 MUX 1 00101 COMMAND DECODER 01100 00011 01011 01010 00000 01001 01000 11111 00111 SETFLSHADD RSTFLSHADD RSTUSRFLSH SETUSRFLSH SAVE REBOOT
00100
VDB
INSTRUCTION REGISTER [LENGTH = 5 BITS]
RPU
MUX 2 TDI TMS TCK TEST ACCESS PORT (TAP) CONTROLLER TDO
Figure 13. JTAG Block Diagram ______________________________________________________________________________________ 37
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Test Access Port (TAP)
Controller State Machine The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCK. See Figure 14 for a diagram of the finite state machine. The possible states are described as follows: Test-Logic-Reset: At power-up, the TAP controller is in the test-logic-reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. This state can be reached from any state by driving TMS high for five clock cycles. Run-Test/Idle: The run-test/idle state is used between scan operations or during specific tests. The instruction register and test data registers remain idle. Select-DR-Scan: All test data registers retain their previous state. With TMS low, a rising edge of TCK moves the controller into the capture-DR state and initiates a scan sequence. TMS high during a rising edge on TCK moves the controller to the select-IR-scan state. Capture-DR: Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test data register remains at its current value. On the rising edge of TCK, the controller goes to the shift-DR state if TMS is low or it goes to the exit1-DR state if TMS is high. Shift-DR: The test data register selected by the current instruction connects between TDI and TDO and shifts data one stage toward its serial output on each rising edge of TCK while TMS is low. On the rising edge of TCK, the controller goes to the exit1-DR state if TMS is high. Exit1-DR: While in this state, a rising edge on TCK puts the controller in the update-DR state. A rising edge on TCK with TMS low puts the controller in the pause-DR state. Pause-DR: Shifting of the test data registers halts while in this state. All test data registers retain their previous state. The controller remains in this state while TMS is low. A rising edge on TCK with TMS high puts the controller in the exit2-DR state. Exit2-DR: A rising edge on TCK with TMS high while in this state puts the controller in the update-DR state. A rising edge on TCK with TMS low enters the shift-DR state.
1
TEST-LOGIC-RESET 0
0
RUN-TEST/IDLE
1
SELECT-DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0
1
SELECT-IR-SCAN 0 1 CAPTURE-IR 0
1
0
SHIFT-IR 1
0
1
EXIT1-IR 0
1
0
PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
0
Figure 14. Tap Controller State Diagram 38 _____________________________________________________________________________________
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Update-DR: A falling edge on TCK while in the updateDR state latches the data from the shift register path of the test data registers into a set of output latches. This prevents changes at the parallel output because of changes in the shift register. On the rising edge of TCK, the controller goes to the run-test/idle state if TMS is low or goes to the select-DR-scan state if TMS is high. Select-IR-Scan: All test data registers retain the previous states. The instruction register remains unchanged during this state. With TMS low, a rising edge on TCK moves the controller into the capture-IR state. TMS high during a rising edge on TCK puts the controller back into the test-logic-reset state. Capture-IR: Use the capture-IR state to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of TCK. If TMS is high on the rising edge of TCK, the controller enters the exit1-IR state. If TMS is low on the rising edge of TCK, the controller enters the shift-IR state. Shift-IR: In this state, the shift register in the instruction register connects between TDI and TDO and shifts data one stage for every rising edge of TCK toward the TDO serial output while TMS is low. The parallel outputs of the instruction register as well as all test data registers remain at the previous states. A rising edge on TCK with TMS high moves the controller to the exit1-IR state. A rising edge on TCK with TMS low keeps the controller in the shift-IR state while moving data one stage through the instruction shift register. Exit1-IR: A rising edge on TCK with TMS low puts the controller in the pause-IR state. If TMS is high on the rising edge of TCK, the controller enters the update-IR state. Pause-IR: Shifting of the instruction shift register halts temporarily. With TMS high, a rising edge on TCK puts the controller in the exit2-IR state. The controller remains in the pause-IR state if TMS is low during a rising edge on TCK. Exit2-IR: A rising edge on TCK with TMS high puts the controller in the update-IR state. The controller loops back to shift-IR if TMS is low during a rising edge of TCK in this state. Update-IR: The instruction code that has been shifted into the instruction shift register latches to the parallel outputs of the instruction register on the falling edge of TCK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on TCK with TMS low puts the controller in the runtest/idle state. With TMS high, the controller enters the select-DR-scan state. Instruction Register The instruction register contains a shift register as well as a latched 5-bit wide parallel output. When the TAP controller enters the shift-IR state, the instruction shift register connects between TDI and TDO. While in the shift-IR state, a rising edge on TCK with TMS low shifts the data one stage toward the serial output at TDO. A rising edge on TCK in the exit1-IR state or the exit2-IR state with TMS high moves the controller to the updateIR state. The falling edge of that same TCK latches the data in the instruction shift register to the instruction register parallel output. Table 28 shows the instructions supported by the MAX16067 and the respective operational binary codes.
MAX16067
Table 28. JTAG Instruction Set
INSTRUCTION BYPASS IDCODE USERCODE LOAD ADDRESS READ DATA WRITE DATA REBOOT SAVE SETFLSHADD RSTFLSHADD SETUSRFLSH RSTUSRFLSH CODE 0x1F 0x00 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C Mandatory instruction code Load manufacturer ID code/part number Load user code Load address register content Read data pointed by current address Write data pointed by current address Reboot FLASH data content into register file Trigger emergency save to flash Flash page access ON Flash page access OFF User flash access ON (must be in flash page already) User flash access OFF (return to flash page) NOTES
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
BYPASS: When the BYPASS instruction is latched into the instruction register, TDI connects to TDO through the 1-bit bypass test data register. This allows data to pass from TDI to TDO without affecting the device's operation. IDCODE: When the IDCODE instruction is latched into the parallel instruction register, the identification data register is selected. The device identification code is loaded into the identification data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially through TDO. During test-logic-reset, the IDCODE instruction is forced into the instruction register. The identification code always has a `1' in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See Table 29. USERCODE: When the USERCODE instruction latches into the parallel instruction register, the user-code data register is selected. The device user-code loads into the user-code data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR can be used to shift the user-code out serially through TDO. See Table 30. This instruction can be used to help identify multiple MAX16067 devices connected in a JTAG chain. LOAD ADDRESS: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16067. When the LOAD ADDRESS instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory address test data register during the shift-DR state. READ DATA: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16067. When the READ instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory read test data register during the shift-DR state. WRITE DATA: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16067. When the WRITE instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory write test data register during the shift-DR state. REBOOT: This is an extension to the standard IEEE 1149.1 instruction set to initiate a software controlled reset to the MAX16067. When the REBOOT instruction latches into the instruction register, the MAX16067 resets and immediately begins the boot-up sequence. SAVE: This is an extension to the standard IEEE 1149.1 instruction set that triggers a fault log. The current ADC conversion results along with fault information are saved to flash depending on the configuration of the Critical Fault Log Control register (r6Dh).
Table 29. 32-Bit Identification Code
MSB VERSION (4 BITS) 0001 PART NUMBER (16 BITS) 1000000000000001 MANUFACTURER (11 BITS) 00011001011 1 LSB FIXED VALUE (1 BIT)
Table 30. 32-Bit User-Code Data
MSB DON'T CARE 00000000000000000 See Table 26 SMBUS SLAVE ID USER ID (r8A[7:0]) LSB
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
SETFLSHADD: This is an extension to the standard IEEE 1149.1 instruction set that allows access to the flash page. Flash registers include ADC conversion results, DACOUT enables, and GPIO input/output data. Use this page to access registers 200h-2FFh. RSTFLSHADD: This is an extension to the standard IEEE 1149.1 instruction set. Use RSTFLSHADD to return to the default page and disable access to the flash page. SETUSRFLSH: This is an extension to the standard IEEE 1149.1 instruction set that allows access to the user flash page. When on the configuration flash page, send the SETUSRFLSH command, all addresses are recognized as flash addresses only. Use this page to access registers 300h-3FFh. RSTUSRFLSH: This is an extension to the standard IEEE 1149.1 instruction set. Use RSTUSRFLSH to return to the configuration flash page and disable access to the user flash. Restrictions When Writing to Flash Flash must be written to 8 bytes at a time. The initial address must be aligned to 8-byte boundaries--the 3 LSBs of the initial address must be `000'. Write the 8 bytes using 8 successive Write Data commands. A write operation requires 122ms for each 8-byte block. After programming a block, check r20h[1] (see Table 31) to make sure the write operation is complete before attempting to write the next block. When it is necessary to hold an EN_OUT_ high or low to prevent premature startup of a power supply before the flash is programmed, connect a resistor from EN_OUT_ to ground or the supply voltage. Avoid connecting a resistor to ground when the output is to be configured as open drain with a separate pullup resistor. When VCC is ramped from 0V, the RESET output is high impedance until VCC reaches 1.4V, at which point RESET goes low. All other outputs are high impedance until VCC reaches 2.7V, then the flash contents are copied into register memory. This takes 150Fs (max) after which the outputs assume their programmed states. The MAX16067 can be programmed in the application circuit by taking into account the following points during circuit design: U The MAX16067 needs to be powered from an intermediate voltage bus or auxiliary voltage supply so programming can occur even when the board's power supplies are off. This could also be achieved by using ORing diodes so that power can be provided through the programming connector. U The SMBus or JTAG bus lines should not connect through a bus multiplexer powered from a voltage rail controlled by the MAX16067. If the device needs to be controlled by an on-board FP, consider connecting the FP to one bus (such as SMBus) and use the other bus for in-circuit programming. U An unprogrammed MAX16067's EN_OUT_s go high impedance. Ensure that this does not cause undesired circuit behavior. If necessary, connect pulldown resistors to prevent power supplies from turning on.
MAX16067
Device Behavior at Power-Up
Programming the MAX16067 in Circuit
Applications Information
When the flash has not been programmed using the JTAG or SMBus interface, the default configuration of the EN_OUT_ outputs is open drain active low. This means that the EN_OUT_ outputs are high impedance.
Unprogrammed Device Behavior
Table 31. RESET State, Flash State, and Reset Reason
REGISTER ADDRESS BIT RANGE [0] r20h [1] [2] [3] [7:4] DESCRIPTION Reset Output State 0 = RESET is low 1 = RESET is high 1 = Flash memory is busy 1 = Last reset asserted due to EN going low 1 = Last reset asserted due to watchdog timeout Not used
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41
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Power to the MAX16067 must be maintained for a specific period of time to ensure a successful flash fault log operation during a fault that removes power to the circuit. Table 32 shows the amount of time required depends on the settings in the fault control register (r6Dh[1:0]). Maintain power for shutdown during fault conditions in applications where the always-on power supply cannot be relied upon by placing a diode and a large capacitor between the voltage source, VIN, and VCC (Figure 15). The capacitor value depends on VIN and the time delay required, tFAULT_SAVE. Use the following formula to calculate the capacitor size: C = (tFAULT_SAVE x ICC(MAX))/(VIN - VDIODE - VUVLO) where the capacitance is in Farads and tFAULT_SAVE is in seconds, ICC(MAX) is 14mA, VDIODE is the voltage drop across the diode, and VUVLO is 2.7V. For example, with a VIN of 14V, a diode drop of 0.7V, and a tFAULT_SAVE of 153ms, the minimum required capacitance is 202FF. Up to three of the programmable outputs (EN_OUT1, EN_OUT2, EN_OUT3) of the MAX16067 can be configured as charge-pump outputs to drive the gates of series-pass n-channel MOSFETS. When driving MOSFETs, these outputs act as simple power switches
Maintaining Power During a Fault Condition
to turn on the voltage supply rails. Approximate the slew rate, SR, using the following formula: SR = ICP/(CGATE + CEXT) where ICP is the 6FA (typ) charge-pump source current, CGATE is the gate capacitance of the MOSFET, and CEXT is the capacitance connected from the gate to ground. If more than three series-pass MOSFETs are required for an application, additional series-pass p-channel MOSFETs can be connected to outputs configured as active-low open drain (Figure 16). Connect a pullup resistor from the gate to the source of the MOSFET, and ensure the absolute maximum ratings of the MAX16067 are not exceeded. An evaluation kit and a graphical user interface (GUI) are available to create a custom configuration for the device. Refer to the MAX16067 Evaluation Kit for configuration. Multiple MAX16067s can be cascaded to increase the number of rails controlled for sequencing and monitoring. There are many ways to cascade the devices depending on the desired behavior. In general, there are several techniques as follows: U Configure a GPIO on each device to be EXTFAULT (open-drain). Externally wire them together with a single pullup resistor. Set register bits r72h[5] and r6Dh[2] to `1'
Configuring the Device
Cascading Multiple MAX16067s
Driving High-Side MOSFET Switches
Table 32. Maximum Write Time
r6Dh[1:0] VALUE 00 01 10 11 Save flags Save ADC readings Do not save anything DESCRIPTION Save flags and ADC readings MAXIMUM WRITE TIME (ms) 153 102 153 --
VIN
VOUT R
VIN C
VCC
MAX16067
MON_
EN_OUT_
GND
MAX16067
Figure 15. Power Circuit for Shutdown During Fault Conditions 42
Figure 16. Connection for a p-Channel Series-Pass MOSFET
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
so that all faults propagate between devices. If a critical fault occurs on one device, EXTFAULT asserts, triggering the nonvolatile fault logger in all cascaded devices and recording a snapshot of all system voltages. U Connect open-drain RESET outputs together to obtain a master system reset signal. U Connect all EN inputs together for a master enable signal. Since the internal timings of each cascaded device are not synchronized, EN_OUT_s placed in the same slot on different devices do not come up in the desired order even if the sequence delays are identical. U Consider using an external FP to control the EN inputs or the software enable bits of cascaded devices, monitoring the RESET outputs as a power-good signal. U For a large number of voltage rails, the MAX16067 can be cascaded hierarchically by using one master device's EN_OUT_s to control the EN inputs of several slave devices. A FP can control power supplies manually without involving the sequencing slot system by controlling EN_OUT_s configured as GPIO. The output of a power supply controlled this way can be monitored using a MON_ input configured as "monitoring only" (see the Monitoring Inputs While Sequencing section). To monitor the supply for critical faults, the FP will need to manually set the critical fault enable bit in r6Eh-r72h after turning on the EN_OUT_, and manually clearing the critical fault enable bit before turning off the EN_OUT_. Bypass DBP and ABP each with a 1FF ceramic capacitor to GND. Bypass VCC with a 10FF capacitor to ground. Avoid routing digital return currents through a sensitive analog area, such as an analog supply input return path or ABP's bypass capacitor ground connection. Use dedicated analog and digital ground planes. Connect the capacitors as close as possible to the device.
Controlling Power Supplies Without Using the Sequencer
MAX16067
Layout and Bypassing
Figure 17. Graphical User Interface Screenshot
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Register Map
FLASH ADDRESS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 230 231 232 233 234 235 236 237 238-23A 23B 23C 23D 23E 23F 240 241-242 REGISTER ADDRESS 000 001 002 003 004 005 006 007 008 009 00A 00B 00C-01A 01B 01C 01D 01E 01F 020 021 030 031 032 033 034 035 036 037 038-03A 03B 03C 03D 03E 03F 040 041-042 READ/ WRITE R R R R R R R R R R R R -- R/W R/W -- R R R/W R R/W R/W -- R/W R/W -- R/W R/W -- R/W R/W R/W R/W R/W R/W -- MON1 ADC output, MSBs MON1 ADC output, LSBs MON2 ADC output, MSBs MON2 ADC output, LSBs MON3 ADC output, MSBs MON3 ADC output, LSBs MON4 ADC output, MSBs MON4 ADC output, LSBs MON5 ADC output, MSBs MON5 ADC output, LSBs MON6 ADC output, MSBs MON6 ADC output, LSBs Reserved Fault register--failed line flags Fault register--failed line flags Reserved GPIO data in (read only) EN_OUT_ as GPIO data in (read only) Flash status/reset output monitor Current sequencer slot EN_OUT_ configuration EN_OUT_ configuration Reserved Charge-pump configuration bits EN_OUT_ as GPIO data out Reserved FAULT dependencies FAULT dependencies Reserved RESET output configuration RESET output dependencies RESET output dependencies GPIO data out GPIO configuration GPIO configuration, ARANEN (ARA Enable) Reserved DESCRIPTION
ADC VALUES, FAULT REGISTERS, GPIOs AS INPUT PORTS--NOT IN FLASH
GPIO AND OUTPUT DEPENDENCIES/CONFIGURATIONS
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Register Map (continued)
FLASH ADDRESS 243 244 245-247 248 249 24A 24B 24C 24D 24E 24F 250 251 252 253 254 255 256 257 258 259 25A-26C FAULT SETUP 26D 26E 26F 270 271 272 06D 06E 06F 070 071 072 R/W R/W R/W R/W -- R/W Save after EXTFAULT fault control Faults causing store in flash Faults causing store in flash Faults causing store in flash Reserved EXTFAULT enable REGISTER ADDRESS 043 044 045-047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A-06C READ/ WRITE R/W R/W -- -- R/W R/W -- R/W R/W -- R/W R/W -- R/W R/W -- R/W R/W -- R/W R/W -- DESCRIPTION
MAX16067
ADC--CONVERSIONS ADCs voltage ranges for MON_ monitoring ADCs voltage ranges for MON_ monitoring Reserved Reserved MON1 OV threshold MON1 UV threshold Reserved MON2 OV threshold MON2 UV threshold Reserved MON3 OV threshold MON3 UV threshold Reserved MON4 OV threshold MON4 UV threshold Reserved MON5 OV threshold MON5 UV threshold Reserved MON6 OV threshold MON6 UV threshold Reserved
INPUT THRESHOLDS
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45
6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Register Map (continued)
FLASH ADDRESS TIMEOUTS 273 274 275 276 277 278 279 27A 27B 27C 27D MISCELLANEOUS 27E 27F 280 281-283 284 285 286 287-289 28A 28B 28C 28D 07E 07F 080 081-083 084 085 086 087-089 08A 08B 08C 08D R/W R/W R/W -- R/W R/W R/W -- R/W R/W R/W R Assign MON_ input from Slot 1 to Slot 6 or for monitoring Assign MON_ input from Slot 1 to Slot 6 or for monitoring Assign MON_ input from Slot 1 to Slot 6 or for monitoring Reserved Assign EN_OUT_ from Slot 1 to Slot 6 Assign EN_OUT_ from Slot 1 to Slot 6 Assign EN_OUT_ from Slot 1 to Slot 6 Reserved Customer use (version) PEC enable/SMBus address Lock bits Revision code 073 074 075 076 077 078 079 07A 07B 07C 07D R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Watchdog independent mode, margin enabled, soft RESET functionality ADC fault deglitch/autoretry configuration WDI toggle/fault timeout, reverse sequencing bit WDRESET, WD timers Sequence delay for Slot 0 Sequence delay for Slot 1 Sequence delay for Slot 2 Sequence delay for Slot 3 Sequence delay for Slot 4 Sequence delay for Slot 5 Sequence delay for Slot 6 REGISTER ADDRESS READ/ WRITE DESCRIPTION
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers
Typical Operating Circuit
MAX16067
+48V IN OUT DC-DC EN IN
LATCH CIRCUIT
IN EN
OUT
IN EN MON1
OUT
IN EN MON2
OUT 3.3V
DC-DC
DC-DC
DC-DC
EN_OUT1 VCC
EN_OUT2
EN_OUT3- EN_OUT6
MON3- MON6 FAULT RESET
MAX16067
EN ABP DBP GND AO
SCL SDA
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 32 TQFN-EP PACKAGE CODE T3255+4 DOCUMENT NO. 21-0140
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6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers MAX16067
Revision History
REVISION NUMBER 0 1 REVISION DATE 10/09 2/10 Initial release Updated Absolute Maximum Ratings and Table 19 DESCRIPTION PAGES CHANGED -- 2, 23
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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